3D Depth Metrology for Semiconductors

Overview

Traditional metrology techniques rely on destructive cross‑sectioning or complex optical setups to measure the depth of micro‑ and nano‑scale features on semiconductor wafers. From January 2022 to June 2024, Sung‑Un Park led the development of a deep‑learning–based 3D depth‑metrology system that estimates the three‑dimensional morphology of semiconductor structures directly from scanning electron microscope (SEM) images. The approach advances metrology by reconstructing depth maps from single or multi‑view SEM images cv.stoz.kr .

Contributions

Depth estimation algorithms: Created neural‑network models that infer the depth of etched features and material layers from 2D SEM images, enabling 3D reconstruction without physical sectioning.

Data synthesis and augmentation: Generated synthetic training data and employed domain adaptation techniques to generalise models across varying SEM imaging conditions and wafer types.

Integration with process control: Worked with equipment engineers to incorporate the depth‑prediction models into real‑time process control for improved uniformity and yield.

Related Patents

Scanning electron microscope image correction – Co‑inventor of a method that calibrates SEM images by acquiring two images before and after preventive maintenance, estimating a calibration factor with a neural network and applying it to correct subsequent images blog.stoz.kr . This calibration is critical for accurate depth estimation.

AI model training using domain similarity – Co‑inventor of a domain‑similarity training framework that fine‑tunes only low‑rank and bias parameters when adapting a pre‑trained model to a new target domain blog.stoz.kr . This technique was employed to adapt depth‑prediction models to different SEM machines and process conditions.

These patents support the 3D depth‑metrology project by providing robust image calibration and efficient model adaptation methods.